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New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor
Archive ouverte : Article de revue
Edité par HAL CCSD ; IOP Publishing
International audience. This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al 0.2 Ga 0.8 N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (V th) of +0.4 V and +0.9 V respectively with ∆V th about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10 −10 A mm −1 , an I ON /I OFF about 10 8 and a breakdown voltage of V BR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.
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